EVENT_CNT_0_INT=Val_0x0, CYCLE_CNT_INT=Val_0x0, EVENT_CNT_3_INT=Val_0x0, EVENT_CNT_2_INT=Val_0x0, EVENT_CNT_1_INT=Val_0x0
Performance Monitor Interrupt Set Register
| EVENT_CNT_0_INT | Enable overflow interrupt request for PMU event counter 0. interrupt request. 0 (Val_0x0): When read, it means the event counter overflow interrupt request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter overflow interrupt request is enabled. When written, it enables the event count overflow |
| EVENT_CNT_1_INT | Enable overflow interrupt request for PMU event counter 1. interrupt request. 0 (Val_0x0): When read, it means the event counter overflow interrupt request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter overflow interrupt request is enabled. When written, it enables the event count overflow |
| EVENT_CNT_2_INT | Enable overflow interrupt request for PMU event counter 2. interrupt request. 0 (Val_0x0): When read, it means the event counter overflow interrupt request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter overflow interrupt request is enabled. When written, it enables the event count overflow |
| EVENT_CNT_3_INT | Enable overflow interrupt request for PMU event counter 3. interrupt request. 0 (Val_0x0): When read, it means the event counter overflow interrupt request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter overflow interrupt request is enabled. When written, it enables the event count overflow |
| CYCLE_CNT_INT | Enable overflow interrupt request for PMU cycle counter. interrupt request. 0 (Val_0x0): When read, it means the cycle counter overflow interrupt request is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the cycle counter overflow interrupt request is enabled. When written, it enables the cycle count overflow |